1. Field of the Invention
This invention relates to a semiconductor memory device and a method of manufacturing the same, and more particularly to a semiconductor memory device having an improved capacitor configuration and a method of manufacturing the same.
2. Description of the Prior Art
In recent years, considerable progress has been made in semiconductor technology, particularly in the high-density integration of semiconductor integrated circuit elements. However, the high-density integration inevitably reduces the capacitor chip area that stores information (electric charge). The reduction of the capacitor chip area causes software errors such that the memory contents of the capacitors are erroneously read, or are easily destroyed by alpha rays or the like. Further, the gate lengths of MOS transistors are reduced, and this deteriorates their reliability.
In order to achieve the high-density integration of semiconductor memory devices while maintaining the large capacitance of the storage capacitors, various techniques have been disclosed. In one of such technique, the storage nodes of polycrystalline silicon or the like are formed on the silicon substrate. Thus, the capacitor areas are enlarged, and the capacitance thereof increases resulting in an increase of storage electric charge.
Specifically, switching transistors are formed on a semiconductor substrate, and storage capacitors are stacked on the memory cell regions of the substrate. One of the electrodes of the thus stacked capacitors is connected to one of the electrodes of the switching transistors. This is a so-called stacked-type memory cell configuration in which the capacitance of the storage capacitors is substantially increased.
The conventional stacked-type memory cell configuration is shown in FIGS. 10a through 10c. In FIG. 10b, an element-isolation insulating film 102 is formed in a p-type silicon substrate 101. In the substrate 101, memory cell regions 100a and 100b are isolated by the film 102. MOSFETs, which are used as switching transistors, are formed in the memory cell regions 100a and 100b. The MOSFETs are constituted respectively by source and drain regions 104a and 104b, source and drain regions 104c and 104d, and gate electrodes 106a and 106b, which are insulated by gate insulating films 105a and 105b. These source and drain regions 104a through 104d consist of n-type diffusion layers, respectively. Further, a first insulating film 107 is formed on the surface of the substrate 101. The film 107 has openings to which parts of the source regions 104a and 104c are exposed. First capacitor electrodes 110a and 110b are formed on the first insulating film 107. One end of the first capacitor electrode 110a is connected to the source region 104a through one of the openings in the film 107. Similarly, one end of the first capacitor electrode 110b is connected to the source region 104c through the other one of the openings in the film 107. On the respective surfaces of the first capacitor electrodes 110a and 110b, capacitor insulating films 111a and 111b are respectively deposited. A second capacitor electrode 112 is formed so as to cover the capacitor insulating films 111a and 111b, and the first insulating film 107, as shown in FIG. 10b.
The above-described stacked-type memory cell is manufactured as follows. Specifically, the source regions 104a and 104c, and the drain regions 104b and 104d, all consisting of n-type diffusion layers, are formed in the p-type silicon substrate 101. Thereafter, the gate electrodes 106a and 106b are formed interposing the gate insulating films 105a and 105b. As a result, the MOSFETs can be formed, which serve as the switching transistors with respect to storage capacitors.
Next, the insulating film 107 of silicon oxide is formed on the entire surface of the substrate 101. Thereafter, storage node contact holes 108a and 108b are made in the film 107. Next, the first capacitor electrodes 110a and 110b of polycrystalline silicon layers having a high-impurity concentration are formed.
Thereafter, the capacitor insulating films 111a and 111b of silicon oxide and the second capacitor electrode 112 of polycrystalline silicon are sequentially deposited on the first capacitor electrodes 110a and 110b.
Next, the substrate 101 is exposed to an atmosphere containing phosphorus, and thermally processed so that phosphorus is diffused into the polycrystalline silicon capacitor electrode 112. As a result, the electrode 112 has a prescribed conductivity. The thus formed second capacitor electrode 112, first capacitor electrodes 110a and 110b, and insulating films 111a and 111b constitute a MOS capacitor. Consequently, a memory cell consisting of MOSFETs and MOS capacitors can be obtained.
In the above-described configuration, the storage node electrode can be extended to the upper portion of the element-isolation region. Further, the steps of the gate electrodes can be utilized to increase the capacitance of the MOS capacitors. The thus obtained capacitance of the stacked-type memory cell can be increased to several times and up to several ten times that of a planar-type memory cell.
However, the miniaturization of chip elements to achieve higher-density integration has been steadily increasing. This inevitably reduces the memory cell chip area of DRAMs. As a result, the prescribed capacitance of storage capacitors can hardly be secured even when a conventional stacked-type memory cell configuration is employed.